1. Field of the Invention
The present invention relates to a semiconductor device, a method of generating a semiconductor device, a method of manufacturing a semiconductor device and a device for generating a semiconductor device. More particularly, the present invention relates to the generation of a pattern used for a semiconductor device capable of reducing electromagnetic interference noise even in the case of driving the device at high speed.
2. Description of Related Art
The use of LSI has spread far and wide, of course, in the field of computers and further in the fields of correspondence equipment such as cellular phones, electric appliances, toys and automobiles. On the other hand, electromagnetic interference (EMI) generated by the above products causes problems of jamming of electric waves in radio and television receiving sets. Further, electromagnetic interference (EMI) generated by the above products could be a cause of malfunction of the other systems.
In order to solve the above problems, it is possible to take measures of filtering or shielding so that the entire product can be covered. However, these countermeasures have disadvantages of increasing the number of parts and also increasing the manufacturing cost, that is, it is difficult to take measures for the entire product. From the above viewpoints, there is a strong demand of suppressing the occurrence of noise from the LSI package.
In the above circumstances, LSI is positioned as a key device of each product. In order to ensure competitiveness of the product, there is a demand of increasing the scale and processing speed of LSI. In order to meet the above demands while the product cycle is being shortened, it is indispensable to automatize to design LSI, and it is necessary to adopt the synchronization designing as a condition of introducing the technique of automatizing to design. When the entire circuit is operated in synchronization with the reference clock, an intensity of the instantaneous electric current is increased so high especially in the case of a large scale and high speed LSI. Accordingly, an increase in the electromagnetic interference is caused.
Since LSI is made fine and the operation frequency of LSI is increased, the countermeasures of solving the problems of latch-up and noise have become important.
In general, in the designing method on the cell base, when diffusion regions and through-holes are formed in the substrate cells, contacts are formed, and the substrate or the well is fixed to a power supply electric potential via the contacts. However, when substrate contacts are added to the basic cells to take measures to solve the problems of latch-up, the chip area is increased.
Therefore, the present inventors proposed the following method (JP-A-2000-208634). In order to prevent the chip area from increasing, substrate contacts are arranged below the electric power supply wiring. When a condenser which bypasses a cell is arranged between the electric power supply wiring and the ground wiring, while an increase in the area of the semiconductor device is being suppressed, the withstanding voltage of latch-up is increased, and the emission of noise is reduced and the malfunction caused by noise coming from the outside is reduced.
Further, the following method is proposed (Japanese Patent Application No. 2001-356279). In order to reduce the occurrence of noise generated from an electric power supply when the semiconductor device is made fine and the operation frequency is increased, a space area in which no layout pattern exists is detected and a region adjacent to the electric power supply wiring region is detected. A decoupling capacitor is arranged in a region obtained when these detected regions are subjected to logic operation.
According to the above method, the decoupling capacitor is arranged being added to the space area, which is a region adjacent to the electric power supply wiring region, in which no layout pattern exists. Therefore, it is possible to further increase the decoupling capacitor.
According to the above methods, it is possible to reduce the noise generated from the electric power supply. However, the semiconductor device has been further made fine and the operation frequency has been further increased at present. Therefore, it is very important to add a much larger decoupling capacitor.
Especially, in the case of designing a semiconductor chip, the development of LSI of which has been completed and the layout of which has been verified, when electromagnetic interference (EMI) is calculated for the entire semiconductor chip and the decoupling capacitor is formed as a countermeasure to reduce EMI, it is necessary to provide a much larger decoupling capacitor.
Even when the decoupling capacitor is increased, the following problems may be encountered. In the case where the layout pattern biases, it is impossible to obtain sufficiently high pattern accuracy for the layer concerned. Further, the pattern accuracy of the upper layer with respect to the layer concerned is affected. Therefore, it is impossible to obtain sufficiently high process accuracy.
Therefore, in some cases, it is desirable that wiring work is automatically conducted while consideration is being given to the process condition again at the final stage of deciding the chip layout.